1. Field of the Invention
The present invention relates to an information processing system and a method for timing adjustment, and more in detail, relates to adjustment of control timing according to the frequency of a clock input signal supplied to an information processing system.
2. Description of the Related Art
In an information processing system, in order to make the life of a system in operation of one-generation design long, it is common practice to upgrade a CPU of the system to something of a higher quality after installing the system. In such a system, unification of the interface between the CPU and a system control section is generally performed so as to cope with the improvement in performance of the CPU.
Improvement in performance of a CPU is often realized by increasing a clock frequency (operating clock frequency). Setting of the clock frequency relating to a CPU is generally conducted by using plural mode pins for setting. However, it needs to dispose such a part as a pull-up resistor, a pull-down resistor, or the like required for mode pin processing, which leads to cost increase. On the other hand, proposed is a computer which makes it possible to enhance in performance of a CPU by changing a clock frequency while realizing cost reduction by eliminating such parts as a mode pin, a pull-up resistor and the like (for instance, refer to Patent Document 1).
Further, in a performance evaluation test or a shipping test of an information processing system, a marginal inspection or test including operating frequency in the system are often carried out. As for the operating frequency, a performance measurement or test is conducted to check the possible extent of increase in operating frequency of the entire system, performance exhibited by application in the system when the operating frequency is increased, or the like.
For instance, in a marginal test of the operating frequency, in order to guarantee operation at a prescribed frequency predetermined by the specification, a test program or the like is carried out with an information processing system at an operating frequency exceeding the prescribed frequency by a predetermined range, that is, at an operating frequency having a margin with respect to the prescribed frequency. In general, a marginal test for the operating frequency is carried out not by changing a clock frequency but also by appropriately changing a supplied voltage, an environmental temperature, or the like.
[Patent Document 1]                Japanese Patent Application Laid-open Hei. 10-289031        
As described above, in upgrade, performance evaluation test/inspection test of an information processing system (CPU), change in the frequency of the clock signal supplied to the CPU is generally carried out.
In recent years, lots of the CPUs have built-in timer systems used in cases where an OS (operating system) in operation keeps time. Therefore, change of the clock frequency with respect to the CPU means change of timer control of the OS, and when a clock frequency is changed, the OS is generally required to be rebuilt.
Since conventional information processing systems, have had few CPUs installed, it has been possible with considerably little labor and cost to change the clock frequency. In recent years, however, the number of CPUs installed on one information processing system has a tendency to increase, and in a multiprocessor system which has installed a great number of CPUs in one system, and in which system runs a separate OS in each CPU, the labor and cost required to calibrate the clock frequency after making changes to the system have remarkably increased.